FPGA Implementation Of RNS Structures

stored or otherwise retained in a retrieval system or transmitted in any form, on any medium or by any means Abstract The objective of this thesis is to investigate the applicability of Field Programmable Gate Arrays (FPGAs) for residue arithmetic applications. FPGAs are programmable devices that can be directly configured by the end user without the use of an integrated circuit fabrication facility. They offer the designer the benefits of custom hardware, eliminating high development costs and manufacturing time. The Residue Number System (RNS) has often been proposed for custom hardware implementation of high throughput DSP algorithms. Residue arithmetic operations are easier to realize using small look-up tables, and since Xilinx FPGAs use look-up tables as configurable logic blocks, they are considered as an ideal choice for RNS based designs. Proper design techniques and effective logic optimization are the key to efficient FPGA implementation. Therefore this thesis proposes a new logic optimization algorithm for FPGA realization of residue arithmetic applications. The algorithm exploits the inherent redundancy present in representing finite rings operations using binary variables. The algorithm uses Binary Decision Diagrams to represent and manipulate logic functions. Residue arithmetic modules encoders, decoder/scalers are implemented in Xilinx FPGA with and without using the logic optimization algorithm. Comparison of results proves the effectiveness of the algorithm. The above modules are simulated and tested. vi Acknowledgments